chipsalliance/verible

verible

✅ Recently maintained

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

1,974Stars
313Forks
+27-day stars

C++ · License unverified · Last push 2026-10-29

Official repository & installation ↗
systemveriloglexeryaccsyntax-treelinterformatterparsersystemverilog-parserstyle-linterhacktoberfest

GitValue · Value evidence

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Provisional rubric; documentation and runtime testing are separate. Missing evidence does not imply low value.

Star history

2025-09-292026-11-02
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2026-11-011,973
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Get the project

git clone https://github.com/chipsalliance/verible.git

Cloning downloads the source. For dependencies and installation, follow the project README.

Related projects & alternative candidates

Related domains do not imply feature parity. Review official documentation and licenses.