SpinalHDL/VexRiscv

VexRiscv

✅ Recently maintained

A FPGA friendly 32 bit RISC-V CPU implementation

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Assembly · MIT · Last push 2026-10-13

Official repository & installation ↗

GitValue · Value evidence

Unscored · Evidence coverage 0%

Provisional rubric; documentation and runtime testing are separate. Missing evidence does not imply low value.

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2025-09-292026-11-03
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Get the project

git clone https://github.com/SpinalHDL/VexRiscv.git

Cloning downloads the source. For dependencies and installation, follow the project README.

Related projects & alternative candidates

Related domains do not imply feature parity. Review official documentation and licenses.