darklife/darkriscv

darkriscv

✅ Recently maintained

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

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+37-day stars

Verilog · BSD-3-Clause · Last push 2026-10-12

Official repository & installation ↗
riscvverilogrisc-vfpgacore

GitValue · Value evidence

Unscored · Evidence coverage 0%

Provisional rubric; documentation and runtime testing are separate. Missing evidence does not imply low value.

Star history

2025-09-292026-11-03
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Get the project

git clone https://github.com/darklife/darkriscv.git

Cloning downloads the source. For dependencies and installation, follow the project README.

Related projects & alternative candidates

Related domains do not imply feature parity. Review official documentation and licenses.