openhwfoundation/cvw

cvw

✅ Recently maintained

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

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SystemVerilog · License unverified · Last push 2026-11-02

Official repository & installation ↗

GitValue · Value evidence

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Provisional rubric; documentation and runtime testing are separate. Missing evidence does not imply low value.

Star history

2025-09-292026-11-03
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Get the project

git clone https://github.com/openhwfoundation/cvw.git

Cloning downloads the source. For dependencies and installation, follow the project README.

Related projects & alternative candidates

Related domains do not imply feature parity. Review official documentation and licenses.