openhwfoundation/cvw

cvw

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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

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SystemVerilog · 许可证待核验 · 最近推送 2026-11-02

官方仓库与安装文档 ↗

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获取项目

git clone https://github.com/openhwfoundation/cvw.git

克隆仅获取源码;依赖与安装步骤请参照项目的 README.

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